Senior Digital Design Ingenieur

Responsibilities

• Study, specification, design and verification of high-quality digital and mixed-signal ICs
• Write digital specifications for mixed-signal ICs, make area and power estimations
• Technical team lead for the digital content of mixed-signal ASICs including interaction with customers, suppliers and the internal ASIC development team
• Lead, attend and present at project/review meetings worldwide
• Coach junior engineers in design, verification and testing of integrated circuits and improve their level of technical expertise and knowledge of the total business
• Work together with international customers and communicate efficiently to successfully complete the project
• Write documentation

• You are a dynamic and highly motivated engineer with at least four years of experience in digital IC design
• You have experience with front-end ASIC or FPGA design in VHDL and/or Verilog and/or SystemVerilog
• You have experience with front-end verification, preferably in SystemVerilog + UVM, to write directed tests, constrained randomized tests and to gather and interpret metrics such as code/condition/FSM/toggle/functional coverage
• You have experience with digital synthesis, logic equivalence checking (LEC) and Static Timing Analysis (STA)
• Experience with UPF and/or CPF and DFT and ATPG is a plus
• Experience with scripting and programming languages such as Python and C is a plus
• Experience with any of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM design, MCU
• You are a self-motivated, efficient professional able to work alone or in teams
• You offer quality and reliability to colleagues, customers and management, willing to share knowledge and able to communicate efficiently
• You are fluent in English, both written and spoken